A TRON processor is any processor with a core based on the free specifications defined by the Japanese TRON Project, an acronym for: The Real-time Operating system Nucleus. The processors are to be the main hardware building block of the TRON Hypernetwork (Highly Functional Distributed System: HFDS), the final goal of the TRON Project. These CPUs use a VLSI (very large scale integration), 32-bit CISC (complex instruction set computer) architecture. Using CISC minimizes the object code size of programs to minimize RAM (random access memory) needs and cost. Several versions exist, made by different firms, mainly for embedded systems, often as cores for devices based on ASIC/ASSP (application-specific integrated circuit, application-specific standard product).
Abstract of paper on Gmicro/FPU (floating-point unit), defines 23 coprocessor instructions; with references, purchase option. [IEEE Micro]
Abstract of paper on Gmicro/100, 32-bit CISC VLSI, based on TRON specification; with references, purchase option. [IEEE Micro]
Abstract of paper on Gmicro/500, with RISC-like dual-pipeline structure to execute basic instructions fast, upward-object-compatible with earlier Gmicro variants; with references, purchase option. [IEEE Micro]
CISC 32-bit processor architecture developed to serve as main hardware building block of the realtime TRON Hypernetwork (Highly Functional Distributed System: HFDS), the ultimate goal of the TRON Project.
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